|Title: Satellite Link Design: A Tutorial|
|Author(s): Aderemi A. Atayero, Matthew K. Luka, Adeyemi A. Alatishe|
|Pages: 1-7||Paper ID: 110904-3232-IJECS-IJENS||Published: August, 2011|
Abstract: The communication link between a satellite and the Earth Station (ES) is exposed to a lot of impairments such as noise, rain and atmospheric attenuations. It is also prone to loss such as those resulting from antenna misalignment and polarization. It is therefore crucial to design for all possible attenuation scenarios before the satellite is deployed. This paper presents the rudiments of a satellite link design in a tutorial form with numerical examples.
|Keywords: Satellite communications, Link analysis, Link design, EIRP, SNR, CNR.|
|Full Text (.pdf) | 589 KB|
|Title: Solar Dish Stirling System and its Economic Prospect in Bangladesh|
|Author(s): Khalid Yousuf Khan, Nahian Al Subri Ivan, Ansari Saeed Ahmed, Abdul Hasib Siddique, Dhrupad Debnath|
|Pages: 8-18||Paper ID: 114104-3737-IJECS-IJENS||Published: August, 2011|
Abstract: This paper presents the design aspect of solar dish starling engine and the prospect of this type of power generation unit in Bangladesh. .In addition, in this paper the variable prospect of solar dish starling engine has been studied. Bangladesh, being a developing country with perpetual shortage of electricity and facing numerous hardships towards generating it, is constantly in search of an alternative source of energy, in which case, Renewable Energy has gained quite a reputation for. Harnessing electricity from solar energy looks more viable among other types of renewable energy in Bangladesh. The solar dish stirling engine technology is new and specially designed to use the solar ray to convert it to usable electricity. The economic aspect also gives this type of engine a great advantage over the existing SHS (Solar Home System). This paper explains working principle, grid connectivity and economic viability of Stirling engine system incorporated with effective design of solar tracking system to enhance the efficiency.
|Keywords: Stirling engine, Grid Connectivity, Modeling, Over Voltage Protection, VAR compensators, NRE, Market Potential.|
|Full Text (.pdf) | 609 KB|
|Title: Assigning IP addresses to Mobile Adhoc Networks nodes by using Backup Source Node|
|Author(s): Hamid Jan, Inayat Ullah|
|Pages: 19-22||Paper ID: 110104-9292-IJECS-IJENS||Published: August, 2011|
Abstract: A Mobile Ad Hoc Network (MANET) nodes represents a system of mobile wireless links. The network's topology is temporary and unpredictable. Such networks can be self organize, or may be connected to the larger Internet. In networks with fixed Infrastructure, hosts rely on centralized servers like DHCP for configuration, but this cannot be supported in MANET because of their dynamic nature and some limitations of DHCP. Many techniques have been proposed to solve this problem. Although the MANET has distributed nature still there are some issues that are solved by using some sort of centralization, like in communication between clusters of MANET nodes is done through central node, which is called Master node. On the basis of this sort of centralization, I propose a solution which is based on the concept of Microsoft Backup Domain Server (BDS). The pool of IP addresses with source node is shared with the first neighbor node. In case the source node gets down, the first neighbor node start assigning IP addresses and IP addresses pool is further shared with another neighbor node. The solution also handles efficiently the merging of networks.
|Keywords: MANET, BDS, IP address, DHCP.|
|Full Text (.pdf) | 168 KB|
|Title: Prioritized Direction based Switch for Bufferless Network on Chip Architecture|
|Author(s): Sajid Gul Khawaja, Mian Hamza Mushtaq, Shoab A. Khan|
|Pages: 23-29||Paper ID: 115704-8383-IJECS-IJENS||Published: August, 2011|
Abstract: This paper represents a bufferless Network on Chip (NoC) architecture for a generic multi-array based architecture. A weighted priority based routing technique will be employed that handles contention based on destination direction. The results will represent the comparative effectiveness of the design with a XY based switch. Matrix multiplication application is tested and mapped as the process entities (PEs) to demonstrate the effectiveness of the NoC design. The NoC architecture is synthesized and tested on FPGA platform as a prototype.
|Keywords: Bufferless, Routing Scheme, NoC, SoC|
|Full Text (.pdf) | 5,346 KB|
|Title: Development of iCU: A Plagiarism Detection Software|
|Author(s): Aderemi A. Atayero, Adeyemi A. Alatishe, Kanyinsola O. Sanusi|
|Pages: 30-35||Paper ID: 111204-3838-IJECS-IJENS||Published: August, 2011|
Abstract: In this paper, we present the design, development and deployment of iCU – a plagiarism detection software. iCU is a software system designed for the detection of plagiarized works. It comprises three main modules with different functions. The first module named file comparison module is designed for use only when there is a contention about two documents that have exactly or nearly the same content. The second module is named the similarity detection module, it is used when an individual is almost certain of the source of a text and works like a search engine. While the third module named global comparison module is meant for checking the extent to which a given piece of work is similar in content to already published works. The developed software works well both online and offline and is easily deployable in an academic environment.
|Keywords: Plagiarism; plagiarism detection; similarity check; copy detection;Turnitin; MOSS; Jplag .|
|Full Text (.pdf) | 404 KB|
|Title: Implementation of Highly-Predictable time-Triggered Cooperative Scheduler using Simple Super Loop Architecture|
|Author(s): Mouaaz Nahas|
|Pages: 36-41||Paper ID: 117404-8989-IJECS-IJENS||Published: August, 2011|
Abstract: Time-Triggered Cooperative (TTC) schedulers provide simple, low-cost software architecture for many embedded applications which have severe resource constraints and require high degrees of predictability. Basic implementations of TTC scheduler can be achieved using Super Loop (SL). Such implementations, however, lack the provision of high predictability in case where tasks running in the system have unpredictable execution durations or various execution periods. This paper reviews the previously developed TTC-SL scheduler and presents an alternative scheduler implementation called “Fixed-Tick TTC-SL scheduler”. The implemented scheduler is evaluated in terms of tick- and task-jitter using a popular family of ARM-based microcontrollers. The results show that such an implementation – although simple – can help to achieve a significant reduction in release jitter at the tick and the ‘top priority’ task at negligible cost in terms of memory overheads.
|Keywords: Super loop, sandwich delay, cyclic executive, time-triggered, cooperative scheduling, tick interval, jitter.|
|Full Text (.pdf) | 488 KB|
|Title: Studying of Wind farm performance at Zafarana Egypt|
|Author(s): Ahmed Fouad A. Aziz|
|Pages: 42-51||Paper ID: 117604-9393-IJECS-IJENS||Published: August, 2011|
Abstract: This paper proposes a study of Zafarana Egypt wind farm performance and verification of its equivalent by studying the load power flow and short circuit for both the detailed model and the equivalent model; also it discusses some possible layouts for offshore wind farms and comparison of method of connections. It was noticed that Zafarana wind farm consists of two types of induction machines, fixed speed and variable speed induction machine. Finally optimal capacitor placement is proposed using the simulation program (ETAP).
|Keywords: Component; Load flow; Short circuit; optimal capacitor placement; DFIG.|
|Full Text (.pdf) | 652 KB|
|Title: Fast Universal Background Model (UBM) Training on GPUs using Compute Unified Device Architecture (CUDA)|
|Author(s): M. Azhari, C. Ergün.|
|Pages: 52-58||Paper ID: 116104-7575-IJECS-IJENS||Published: August, 2011|
Abstract: Universal Background Modeling (UBM) is an alternative hypothesized modeling that is used extensively in Speaker Verification (SV) systems. Training the background models from large speech data requires a significant amount of memory and computational load. In this paper a parallel implementation of speaker verification system based on Gaussian Mixture Modeling – Universal Background Modeling (GMM – UBM) designed for many-core architecture of NVIDIA’s Graphics Processing Units (GPU) using CUDA single instruction multiple threads (SIMT) model is presented. CUDA implementation of these algorithms is designed in such a way that the speed of computation of the algorithm increases with number of GPU cores. In this experiment 30 times speedup for k-means clustering and 16 times speedup for Expectation Maximization (EM) was achieved for an input of about 350K frames of 16 dimensions and 1024 mixtures on GeForce GTX 570 (NVIDIA Fermi Series) with 480 cores when compared to a single threaded implementation on the traditional CPU.
|Keywords: Compute Unified Device Architecture (CUDA), Expectation Maximization (EM), Speaker Verification, Universal Background Model (UBM).|
|Full Text (.pdf) | 537 KB|
|Title: Fuzzy Control of a Nonlinear Deterministic System for Different Operating Points|
|Author(s): Gonca Ozmen Koca, Cafer Bal|
|Pages: 59-63||Paper ID: 1110404-9292-IJECS-IJENS||Published: August, 2011|
Abstract: In this paper, a robust control system with the fuzzy logic approach is proposed. Two linear controllers which have a good performance in the upper and lower operating points are designed in order to control a nonlinear deterministic system. The performances of linear controllers are investigated in different operating points. A fuzzy logic controller, generally preferred when the linear controllers are not able to control the system with a satisfactory performance, is examined for the nonlinear system in different operating points. The obtained results in the Matlab/SIMULINK environment show the efficiency of the proposed fuzzy controller for the nonlinear system without the readjustment of the control parameter for each different operating point.
|Keywords: Fuzzy logic, nonlinear system, robust control.|
|Full Text (.pdf) | 414 KB|