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Title: Low Power Optimization Technique and a genetic minimization algorithm for variable ordering of BDD mapped VLSI Circuits
Author(s): Manu Bansal, Alpana Agarwal
Pages: 1-6 Paper ID:173605-8282-IJECS-IJENS Published: October, 2017
Abstract: Ordered binary decision diagrams (BDDs) yield a data structure for switching functions that has been proven to be very useful in sloving many of the problems in VLSI CAD. BDD-based calculations is the variable ordering problem which addresses the major problem of finding an ordering of the input variables which minimizes the size of the BDD-representation. In this paper, the use of genetic algorithms to improve the variable ordering of a given BDD is implemented and experimental studies are reported. This paper proposes genetic algorithm with three crossover operators namely order, cycle and partially mapped (PMX) crossovers for minimization of shared ordered Binary Decision Diagrams (BDDs). The implementation was done using C++ codes and the simulation was carried out on the BUDDY 2.4 package on Ubuntu 12.04. The observations for the node count show that the node count reduction, maximum 74% (for 8-adder) is better obtained by using PMX operators both for the LGSynth93 benchmark circuits as well as multi-input adders. The power estimation was done for the circuits and a maximum of about 99.9% power reduction has been obtained by the proposed technique in case of Multi-input adders, especially in case of 6-adder and 8-adder. The proposed Genetic algorithm is found to be suitable for multi-input multi-output (MIMO) VLSI circuits.
Keywords: Genetic Algorithm, BDDs, Order, Cycle, Partially Mapped.
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